Prior to the advent of high-speed technology exemplified by magnetic bubble devices and semiconductor shift registers, BCH-type encoders and decoders utilized a distributed series of exclusive OR gates to effect binary division which, in turn, generated encoder parity check bits and the decoder syndrome.
In my paper, entitled "The Design and Embodiment of Magnetic Domain Encoders for Single-Error Correcting Decoders for Cyclic Block Codes," published in the February, 1972 issue of the Bell System Technical Journal, a single exclusive OR gate arrangement was described to effect binary division. However, the topology of the arrangement was specific to magnetic domain technology.
In my recent U.S. Pat. No. 4,312,069 issued Jan. 19, 1982, the gate arrangement is generalized by utilizing semiconductor shift registers to accomplish binary division. Shift-in to the registers of the encoder occurs at the input data word rate and shift-out occurs at the output code word rate. The obverse obtains in the decoder. With the generalized arrangement, it is feasible to provide a synchronized, single error correcting data transmission system utilizing serial binary division for generating parity bits at the encoder and iteratively shifted versions of the syndrome at the decoder. Error correcting information is obtained by serial comparison of the iteratively shifted versions of the syndrome with the characteristic word of the code. Moreover, to insure the encoder functions properly whenever the number of parity bits is small, certain output buffer registers are segmented. These segmented registers have lengths that satisfy the data synchronism requirement as well as the shift register requirement that each of the storage means be shifting in or shifting out during predefined intervals within an encoding cycle.
It is well-known that noise on many telecommunication facilities which carry high-speed data, such as multipair cable, causes errors that typically occur in bursts. Conventional burst error correction techniques are available to mitigate errors: however, these techniques are not only complex but introduce considerable delay in the decoding process.
While single error correcting procedures of the type described in the aforementioned paper and patent prove to be of little direct value to correct for error bursts, it is possible to generalize the encoder and decoder structures, as well as the accompanying methodology, to correct for bursts of errors which have a presumed maximum length. Thus, the simplicity and ease of implementing single error correcting codes is retained within the burst error environment.